Fundamentals of Logic Design, Enhanced 7th edition

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Charles H. Roth, Jr., Larry L. Kinney, and Eugene B. John
Publisher: Cengage Learning

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  • Chapter 1: Introduction Number Systems and Conversations
    • 1.1: Digital Systems and Switching Circuits
    • 1.2: Number Systems and Conversion (12)
    • 1.3: Binary Arithmetic (4)
    • 1.4: Representation of Negative Numbers (5)
    • 1.5: Binary Codes (8)
    • 1: Problems
    • 1: Chapter Quiz

  • Chapter 2: Boolean Algebra
    • 2.1: Introduction
    • 2.2: Basic Operations
    • 2.3: Boolean Expressions and Truth Tables (3)
    • 2.4: Basic Theorems
    • 2.5: Thermal Commutative, Associative, Distributive, and DeMorgan's Laws (2)
    • 2.6: Simplification Theorems (12)
    • 2.7: Multiplying Out and Factoring (6)
    • 2.8: Complementing Boolean Expressions
    • 2: Problems
    • 2: Chapter Quiz

  • Chapter 3: Boolean Algebra (Continued)
    • 3.1: Multiplying Out and Factoring Expressions (4)
    • 3.2: Exclusive-OR and Equivalence Operations
    • 3.3: The Consensus Theorem (2)
    • 3.4: Algebraic Simplification of Switching Expressions (10)
    • 3.5: Proving Validity of an Equation (2)
    • 3: Problems
    • 3: Chapter Quiz

  • Chapter 4: Applications of Boolean Algebra Minterm and Maxterm Expansions
    • 4.1: Conversion of English Sentences to Boolean Equations (4)
    • 4.2: Combinational Logic Design Using a Truth Table (5)
    • 4.3: Minterm and Maxterm Expansions (4)
    • 4.4: General Minterm and Maxterm Expansions (6)
    • 4.5: Incompletely Specified Functions (3)
    • 4.6: Examples of Truth Table Construction (6)
    • 4.7: Design of Binary Adders and Subtracters
    • 4: Problems
    • 4: Chapter Quiz

  • Chapter 5: Karnaugh Maps
    • 5.1: Minimum Forms of Switching Functions
    • 5.2: Two- and Three-Variable Karnaugh Maps (5)
    • 5.3: Four-Variable Karnaugh Maps (8)
    • 5.4: Determination of Minimum Expressions Using Essential Prime Implicants (6)
    • 5.5: Five-Variable Karnaugh Maps (4)
    • 5.6: Other Uses of Karnaugh Maps
    • 5.7: Other Forms of Karnaugh Maps
    • 5: Problems
    • 5: Chapter Quiz

  • Chapter 6: Quine-McCluskey Method
    • 6.1: Determination of Prime Implicants (7)
    • 6.2: The Prime Implicant Chart (5)
    • 6.3: Petrick's Method (2)
    • 6.4: Simplification of Incompletely Specified Functions
    • 6.5: Simplification Using Map-Entered Variables (1)
    • 6.6: Conclusion
    • 6: Problems
    • 6: Chapter Quiz

  • Chapter 7: Multi-Level Gate Circuits NAND and NOR Gates
    • 7.1: Multi-Level Gate Circuits (6)
    • 7.2: NAND and NOR Gates (1)
    • 7.3: Design of Two-Level NAND- and NOR-Gate Circuits (10)
    • 7.4: Design of Multi-Level NAND- and NOR-Gate Circuits
    • 7.5: Circuit Conversion Using Alternative Gate Symbols (13)
    • 7.6: Design of Two-Level, Multiple-Output Circuits
    • 7.7: Multiple-Output NAND- and NOR-Gate Circuits
    • 7: Problems
    • 7: Chapter Quiz

  • Chapter 8: Combinational Circuit Design and Simulation Using Gates
    • 8.1: Review of Combinational Circuit Design
    • 8.2: Design of Circuits with Limited Gate Fan-In
    • 8.3: Gate Delays and Timing Diagrams (3)
    • 8.4: Hazards in Combinational Logic (6)
    • 8.5: Simulation and Testing of Logic Circuits (2)
    • 8: Problems
    • 8: Chapter Quiz

  • Chapter 9: Multiplexers, Decoders, and Programmable Logic Devices
    • 9.1: Introduction
    • 9.2: Multiplexers (10)
    • 9.3: Three-State Buffers
    • 9.4: Decoders and Encoders (6)
    • 9.5: Read-Only Memories
    • 9.6: Programmable Logic Devices (5)
    • 9.7: Complex Programmable Logic Devices
    • 9.8: Field-Programmable Gate Arrays (4)
    • 9: Problems
    • 9: Chapter Quiz

  • Chapter 10: Introduction to VHDL
    • 10.1: VHDL Description of Combinational Circuits (3)
    • 10.2: VHDL Models for Multiplexers (1)
    • 10.3: VHDL Modules (1)
    • 10.4: Signals and Constants
    • 10.5: Arrays
    • 10.6: VHDL Operators (2)
    • 10.7: Packages and Libraries
    • 10.8: IEEE Standard Logic (2)
    • 10.9: Compilation and Simulation of VHDL Code
    • 10: Problems
    • 10: Chapter Quiz

  • Chapter 11: Latches and Flip-Flops
    • 11.1: Introduction (1)
    • 11.2: Set-Reset Latch (3)
    • 11.3: Gated Latches (2)
    • 11.4: Edge-Triggered D Flip-Flop (3)
    • 11.5: S-R Flip-Flop (3)
    • 11.6: J-K Flip-Flop (2)
    • 11.7: T Flip-Flop (4)
    • 11.8: Flip-Flops with Additional Inputs (2)
    • 11.9: Asynchronous Sequential Circuits
    • 11.10: Summary
    • 11: Problems
    • 11: Chapter Quiz

  • Chapter 12: Registers and Counters
    • 12.1: Registers and Register Transfers (1)
    • 12.2: Shift Registers (6)
    • 12.3: Design of Binary Counters (1)
    • 12.4: Counters for Other Sequences (9)
    • 12.5: Counter Design Using S-R and J-K Flip-Flops (7)
    • 12.6: Derivation of Flip-Flop Input Equations—Summary
    • 12: Problems
    • 12: Chapter Quiz

  • Chapter 13: Analysis of Clocked Sequential Circuits
    • 13.1: A Sequential Parity Checker
    • 13.2: Analysis by Signal Tracing and Timing Charts
    • 13.3: State Tables and Graphs (17)
    • 13.4: General Models for Sequential Circuits (1)
    • 13: Problems
    • 13: Chapter Quiz

  • Chapter 14: Derivation of State Graphs and Tables
    • 14.1: Design of a Sequence Detector (2)
    • 14.2: More Complex Design Problems (1)
    • 14.3: Guidelines for Construction of State Graphs (28)
    • 14.4: Serial Data Code Conversion (1)
    • 14.5: Alphanumeric State Graph Notation
    • 14.6: Incompletely Specified State Tables (5)
    • 14: Problems
    • 14: Chapter Quiz

  • Chapter 15: Reduction of State Tables State Assignment
    • 15.1: Elimination of Redundant States (3)
    • 15.2: Equivalent States (1)
    • 15.3: Determination of State Equivalence Using an Implication Table (6)
    • 15.4: Equivalent Sequential Circuits
    • 15.5: Reducing Incompletely Specified State Tables (3)
    • 15.6: Derivation of Flip-Flop Input Equations (4)
    • 15.7: Equivalent State Assignments
    • 15.8: Guidelines for State Assignment (2)
    • 15.9: Using a One-Hot State Assignment (3)
    • 15: Problems
    • 15: Chapter Quiz

  • Chapter 16: Sequential Circuit Design
    • 16.1: Summary of Design Procedure for Sequential Circuits
    • 16.2: Design Example—Code Converter (5)
    • 16.3: Design of Iterative Circuits (3)
    • 16.4: Design of Sequential Circuits Using ROMs and PLAs (3)
    • 16.5: Sequential Circuit Design Using CPLDs
    • 16.6: Sequential Circuit Design Using FPGAs
    • 16.7: Simulation and Testing of Sequential Circuits
    • 16.8: Overview of Computer-Aided Design
    • 16: Problems
    • 16: Chapter Quiz

  • Chapter 17: VHDL for Sequential Logic
    • 17.1: Modeling Flip-Flops Using VHDL Processes (3)
    • 17.2: Modeling Registers and Counters Using VHDL Processes (3)
    • 17.3: Modeling Combinational Logic Using VHDL Processes (8)
    • 17.4: Modeling a Sequential Machine (2)
    • 17.5: Synthesis of VHDL Code
    • 17.6: More About Processes and Sequential Statements
    • 17: Problems
    • 17: Chapter Quiz

  • Chapter 18: Circuits for Arithmetic Operations
    • 18.1: Serial Adder with Accumulator (8)
    • 18.2: Design of a Binary Multiplier (5)
    • 18.3: Design of a Binary Divider (4)
    • 18: Problems
    • 18: Chapter Quiz

  • Chapter 19: State Machine Design with SM Charts
    • 19.1: State Machine Charts
    • 19.2: Derivation of SM Charts
    • 19.3: Realization of SM Charts (15)
    • 19: Problems
    • 19: Chapter Quiz

  • Chapter 20: VHDL for Digital System Design
    • 20.1: VHDL Code for a Serial Adder (3)
    • 20.2: VHDL Code for a Binary Multiplier (2)
    • 20.3: VHDL Code for a Binary Divider
    • 20.4: VHDL Code for a Dice Game Simulator (1)
    • 20.5: Concluding Remarks
    • 20: Problems
    • 20: Chapter Quiz


Updated with modern coverage, a streamlined presentation, and excellent companion software, this enhanced 7th edition of Fundamentals of Logic Design achieves yet again an unmatched balance between theory and application. Authors Charles H. Roth, Jr. and Larry L. Kinney, and contributing author, Eugene B. John, carefully present the theory that is necessary for understanding the fundamental concepts of logic design while not overwhelming students with the mathematics of switching theory. Divided into 20 easy-to-grasp study units, the book covers such fundamental concepts as Boolean algebra, logic gates design, flip-flops, and state machines. By combining flip-flops with networks of logic gates, students will learn to design counters, adders, sequence detectors, and simple digital systems. After covering the basics, this text presents modern design techniques using programmable logic devices and the VHDL hardware description language.

Meet the Authors

Charles H. Roth, Jr., University of Texas, Austin
Charles Roth is Professor Emeritus in Electrical and Computer Engineering at the University of Texas at Austin, where he taught Digital Design for more than four decades. In addition to this successful book, Dr. Roth has co-authored Digital Systems Design Using VHDL and Digital Systems Design Using Verilog.

Larry L. Kinney, University of Minnesota
Larry L. Kinney is a Professor and Director of Undergraduate Studies at the University of Minnesota. He received his Ph.D. in Electrical Engineering from the University of Iowa. His research has focused on digital system and digital computer design, specifically concurrent error detection techniques, testing of logic and design, distributed computer systems, computer architectures, error detecting/correcting codes and applications of microprocessors.

Eugene B. John, University of Texas, Austin
Eugene B. John is a Professor in Electrical and Computer Engineering at the University of Texas at Austin. His areas of interest include VLSI design, computer architecture, energy efficient computing, energy efficient hardware for machine learning and artificial intelligence and hardware security.

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Group Quantity Questions
Chapter 1: Introduction Number Systems and Conversations
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1.2 12 001 002 003 004 010 011 012 013 013.EP 014 016 023
1.3 4 005 006 017 020
1.4 5 007 008 022 036 040
1.5 8 009 028 031 032 033 033.EP 034 035
Chapter 2: Boolean Algebra
2.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
2.3 3 019 019.EP 021
2.5 2 002 015
2.6 12 008 009 010 011 012 016 017 018 027 027.EP 028 030
2.7 6 005 006 007 014 022 023
Chapter 3: Boolean Algebra (Continued)
3.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
3.1 4 006 007 014 015
3.3 2 021 024
3.4 10 011 013 022 023 025 026 030 034 035 036
3.5 2 032 038
Chapter 4: Applications of Boolean Algebra Minterm and Maxterm Expansions
4.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
4.1 4 001 002 020 020.EP
4.2 5 004 021 022 037 038
4.3 4 007 008 025 026
4.4 6 009 010 027 028 029 030
4.5 3 005 032 033
4.6 6 013 014 014.EP 016 017 018
Chapter 5: Karnaugh Maps
5.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020
5.2 5 003 014 015 016 020
5.3 8 004 012 017 017.EP 018 028 028.EP 030
5.4 6 007 008 024 025 031 032
5.5 4 009 033 043 044
Chapter 6: Quine-McCluskey Method
6.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
6.1 7 002 004 007 009 010 012 020
6.2 5 003 008 018 021 022
6.3 2 005 023
6.5 1 024
Chapter 7: Multi-Level Gate Circuits NAND and NOR Gates
7.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020
7.1 6 015 016 017 022 042 043
7.2 1 030
7.3 10 004 004.EP 005 006 007 020 021 028 033 033.EP
7.5 13 019 023 027 029 031 032 036 037 038 039 040 041 044
Chapter 8: Combinational Circuit Design and Simulation Using Gates
8.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
8.3 3 001 010 012
8.4 6 002 002.EP 003 009 011 011.EP
8.5 2 004 005
Chapter 9: Multiplexers, Decoders, and Programmable Logic Devices
9.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
9.2 10 015 016 017 019 021 022 036 037 039 040
9.4 6 005 024 025 026 046 046.EP
9.6 5 029 029.EP 030 032 033
9.8 4 013 041 042 043
Chapter 10: Introduction to VHDL
10.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
10.1 3 001 002 012
10.2 1 003
10.3 1 010
10.6 2 006 014
10.8 2 013 016
Chapter 11: Latches and Flip-Flops
11.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
11.1 1 001
11.2 3 002 014 014.EP
11.3 2 004 018
11.4 3 005 019 023
11.5 3 011 016 021
11.6 2 007 022
11.7 4 017 017.EP 024 025
11.8 2 008 026
Chapter 12: Registers and Counters
12.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
12.1 1 039
12.2 6 003 011 013 028 029 030
12.3 1 016
12.4 9 006 006.EP 007 008 009 025 035 035.EP 036
12.5 7 017 018 020 023 024 032 033
Chapter 13: Analysis of Clocked Sequential Circuits
13.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019
13.3 17 005 008 008.EP 009 011 012 013 014 018 019 019.EP 021 022 023 024 028 029
13.4 1 006
Chapter 14: Derivation of State Graphs and Tables
14.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
14.1 2 004 005
14.2 1 006
14.3 28 010 012 013 014 015 016 017 018 019 020 020.EP 025 029 030 030.EP 031 032 033 034 035 036 037 038 039 040 041 042 045
14.4 1 009
14.6 5 047 048 049 050 051
Chapter 15: Reduction of State Tables State Assignment
15.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
15.1 3 012 013 014
15.2 1 020
15.3 6 002 003 017 018 019 021
15.5 3 004 004.EP 045
15.6 4 009 038 038.EP 039
15.8 2 007 036
15.9 3 034 035 037
Chapter 16: Sequential Circuit Design
16.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
16.2 5 027 028 030 032 032.EP
16.3 3 019 019.EP 020
16.4 3 015 016 022
Chapter 17: VHDL for Sequential Logic
17.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
17.1 3 001 009 011
17.2 3 003 012 018
17.3 8 007 014 016 024 025 026 027 030
17.4 2 005 028
Chapter 18: Circuits for Arithmetic Operations
18.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
18.1 8 008 008.EP 010 012 013 014 020 020.EP
18.2 5 005 017 021 027 031
18.3 4 006 007 018 033
Chapter 19: State Machine Design with SM Charts
19.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
19.3 15 003 004 006 009 010 012 015 017 018 019 021 024 027 029 031
Chapter 20: VHDL for Digital System Design
20.CQ 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018
20.1 3 002 004 006
20.2 2 001 010
20.4 1 008
Total 397 (366)